diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-09-14 21:28:17 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-14 21:28:17 +0000 |
| commit | 5b46d62c4459dbfd56bb6ac650a271cd02365092 (patch) | |
| tree | e1b62b07257e474ed8f8edab2752d5aa3ca3a489 | |
| parent | 3b8b2ca3a8521d5a95022bf5fc9d33b9f9d28b2a (diff) | |
Add predicate and 's' bit operands to PICADD instruction lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 47d68fa80d..067d1a6bf8 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1349,6 +1349,11 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); + // Add predicate operands. + AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); + AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); + // Add 's' bit operand (always reg0 for this) + AddInst.addOperand(MCOperand::CreateReg(0)); OutStreamer.EmitInstruction(AddInst); return; } |