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author | Justin Holewinski <justin.holewinski@gmail.com> | 2011-04-28 00:19:51 +0000 |
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committer | Justin Holewinski <justin.holewinski@gmail.com> | 2011-04-28 00:19:51 +0000 |
commit | 5a3cb924c6b9685429042e189d743f70a775548c (patch) | |
tree | 2cfef35ebd4b52b79f6bf7ef45d5fb44d261ad24 | |
parent | 9583a86ba822602e25a8fcc8e9035ac5a4f9ce8c (diff) |
PTX: support for bitwise operations on predicates
- selection of bitwise preds (AND, OR, XOR)
- new bitwise.ll test
Patch by Dan Bailey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130353 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/PTX/PTXInstrInfo.td | 8 | ||||
-rw-r--r-- | test/CodeGen/PTX/bitwise.ll | 24 |
2 files changed, 32 insertions, 0 deletions
diff --git a/lib/Target/PTX/PTXInstrInfo.td b/lib/Target/PTX/PTXInstrInfo.td index c124c03896..921933e6ae 100644 --- a/lib/Target/PTX/PTXInstrInfo.td +++ b/lib/Target/PTX/PTXInstrInfo.td @@ -258,6 +258,14 @@ multiclass INT3<string opcstr, SDNode opnode> { } multiclass PTX_LOGIC<string opcstr, SDNode opnode> { + def ripreds : InstPTX<(outs Preds:$d), + (ins Preds:$a, i1imm:$b), + !strconcat(opcstr, ".pred\t$d, $a, $b"), + [(set Preds:$d, (opnode Preds:$a, imm:$b))]>; + def rrpreds : InstPTX<(outs Preds:$d), + (ins Preds:$a, Preds:$b), + !strconcat(opcstr, ".pred\t$d, $a, $b"), + [(set Preds:$d, (opnode Preds:$a, Preds:$b))]>; def rr16 : InstPTX<(outs RRegu16:$d), (ins RRegu16:$a, RRegu16:$b), !strconcat(opcstr, ".b16\t$d, $a, $b"), diff --git a/test/CodeGen/PTX/bitwise.ll b/test/CodeGen/PTX/bitwise.ll new file mode 100644 index 0000000000..dbc77e5333 --- /dev/null +++ b/test/CodeGen/PTX/bitwise.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +; preds + +define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) { +; CHECK: and.pred p0, p1, p2 + %c = and i1 %x, %y + %d = zext i1 %c to i32 + ret i32 %d +} + +define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) { +; CHECK: or.pred p0, p1, p2 + %a = or i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) { +; CHECK: xor.pred p0, p1, p2 + %a = xor i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} |