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authorEvan Cheng <evan.cheng@apple.com>2005-12-13 00:25:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2005-12-13 00:25:07 +0000
commit5a38e0210dce709988e5af69bdd32eec87325e0c (patch)
tree0a659b7cf96bc034b9a4e9434f7208503b04b2c1
parent9b6b642647889ef3c387c8bcbc0a58fd522c4ea8 (diff)
Missed a couple redundant explicit type casts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24684 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/X86/X86InstrInfo.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a3c16c70ec..736b8a90d1 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -354,15 +354,15 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
"out{b} {%al, $port|$port, %AL}",
- [(writeport AL, (i16 i16immZExt8:$port))]>,
+ [(writeport AL, i16immZExt8:$port)]>,
Imp<[AL], []>;
def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{w} {%ax, $port|$port, %AX}",
- [(writeport AX, (i16 i16immZExt8:$port))]>,
+ [(writeport AX, i16immZExt8:$port)]>,
Imp<[AX], []>, OpSize;
def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{l} {%eax, $port|$port, %EAX}",
- [(writeport EAX, (i16 i16immZExt8:$port))]>,
+ [(writeport EAX, i16immZExt8:$port)]>,
Imp<[EAX], []>;
//===----------------------------------------------------------------------===//