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authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-15 05:09:20 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-15 05:09:20 +0000
commit59f26aadce1bb985b9befe841fc106c891e1c728 (patch)
treed6416e66d691a368fa9e14ee67f3186797971f94
parent31bfd9bc45b705d03df0c43d8ca8c7a0ecc126b3 (diff)
Use a SetTheory instance to expand register lists in register classes.
This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133043 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--utils/TableGen/CodeGenRegisters.cpp9
-rw-r--r--utils/TableGen/CodeGenRegisters.h9
2 files changed, 13 insertions, 5 deletions
diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp
index 1df9cc10bf..37952fc36a 100644
--- a/utils/TableGen/CodeGenRegisters.cpp
+++ b/utils/TableGen/CodeGenRegisters.cpp
@@ -172,9 +172,9 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
}
assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
- Elements = R->getValueAsListOfDefs("MemberList");
- for (unsigned i = 0, e = Elements.size(); i != e; ++i)
- Members.insert(RegBank.getReg(Elements[i]));
+ Elements = RegBank.getSets().expand(R);
+ for (unsigned i = 0, e = Elements->size(); i != e; ++i)
+ Members.insert(RegBank.getReg((*Elements)[i]));
// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
ListInit *SRC = R->getValueAsListInit("SubRegClasses");
@@ -240,6 +240,9 @@ const std::string &CodeGenRegisterClass::getName() const {
//===----------------------------------------------------------------------===//
CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
+ // Configure register Sets to understand register classes.
+ Sets.addFieldExpander("RegisterClass", "MemberList");
+
// Read in the user-defined (named) sub-register indices.
// More indices will be synthesized later.
SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h
index d096ccd3f3..55f0b9b3aa 100644
--- a/utils/TableGen/CodeGenRegisters.h
+++ b/utils/TableGen/CodeGenRegisters.h
@@ -16,6 +16,7 @@
#define CODEGEN_REGISTERS_H
#include "Record.h"
+#include "SetTheory.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
@@ -84,7 +85,7 @@ namespace llvm {
class CodeGenRegisterClass {
CodeGenRegister::Set Members;
- std::vector<Record*> Elements;
+ const std::vector<Record*> *Elements;
public:
Record *TheDef;
std::string Namespace;
@@ -125,7 +126,7 @@ namespace llvm {
// Returns an ordered list of class members.
// The order of registers is the same as in the .td file.
ArrayRef<Record*> getOrder() const {
- return Elements;
+ return *Elements;
}
CodeGenRegisterClass(CodeGenRegBank&, Record *R);
@@ -135,6 +136,8 @@ namespace llvm {
// them.
class CodeGenRegBank {
RecordKeeper &Records;
+ SetTheory Sets;
+
std::vector<Record*> SubRegIndices;
unsigned NumNamedIndices;
std::vector<CodeGenRegister> Registers;
@@ -154,6 +157,8 @@ namespace llvm {
public:
CodeGenRegBank(RecordKeeper&);
+ SetTheory &getSets() { return Sets; }
+
// Sub-register indices. The first NumNamedIndices are defined by the user
// in the .td files. The rest are synthesized such that all sub-registers
// have a unique name.