diff options
author | Chris Lattner <sabre@nondot.org> | 2005-02-04 18:39:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2005-02-04 18:39:19 +0000 |
commit | 595dc5408ad809b9a9a417db275c43242e54b8dc (patch) | |
tree | 594179e2390f8475306dd9785f24c153f8eea455 | |
parent | 440e688b8d064fcaf0e4b4647a695e2322c04f2e (diff) |
Fix a case where were incorrectly compiled cast from short to int on 64-bit
targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20030 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 63530deac7..1e976e3f68 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1071,9 +1071,11 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { Result = PromoteOp(Node->getOperand(0)); // The high bits are not guaranteed to be anything. Insert an extend. if (Node->getOpcode() == ISD::SIGN_EXTEND) - Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, VT); + Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, + Node->getOperand(0).getValueType()); else - Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, VT); + Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, NVT, Result, + Node->getOperand(0).getValueType()); break; } break; |