propagate struct size and alignment of byval arguments to the DAG

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40986 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 40 insertions, 4 deletions

diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h
index 959d0528c6..9c776131b5 100644
--- a/include/llvm/CodeGen/CallingConvLower.h
+++ b/include/llvm/CodeGen/CallingConvLower.h
@@ -190,6 +190,10 @@ public:
     StackOffset += Size;
     return Result;
   }
+
+  void HandleStruct(unsigned ValNo, MVT::ValueType ValVT,
+                    MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
+                    unsigned ArgFlags);
 private:
   /// MarkAllocated - Mark a register and all of its aliases as allocated.
   void MarkAllocated(unsigned Reg);
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 3502e89501..b0278cbc5b 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -68,6 +68,10 @@ namespace ISD {
     ByValOffs         = 4,
     Nest              = 1<<5,  ///< Parameter is nested function static chain
     NestOffs          = 5,
+    ByValAlign        = 0xF << 6, //< The alignment of the struct
+    ByValAlignOffs    = 6,
+    ByValSize         = 0x1ffff << 10, //< The size of the struct
+    ByValSizeOffs     = 10,
     OrigAlignment     = 0x1F<<27,
     OrigAlignmentOffs = 27
   };
@@ -200,6 +204,10 @@ namespace ISD {
     /// Bit 0 - signness
     /// Bit 1 - 'inreg' attribute
     /// Bit 2 - 'sret' attribute
+    /// Bit 4 - 'byval' attribute
+    /// Bit 5 - 'nest' attribute
+    /// Bit 6-9 - alignment of byval structures
+    /// Bit 10-26 - size of byval structures
     /// Bits 31:27 - argument ABI alignment in the first argument piece and
     /// alignment '1' in other argument pieces.
     CALL,
diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index defbe3416e..bcd132fb03 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -28,6 +28,17 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
   UsedRegs.resize(MRI.getNumRegs());
 }
 
+void CCState::HandleStruct(unsigned ValNo, MVT::ValueType ValVT,
+                           MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
+                           unsigned ArgFlags) {
+  unsigned Align  = 1 << ((ArgFlags & ISD::ParamFlags::ByValAlign) >>
+                          ISD::ParamFlags::ByValAlignOffs);
+  unsigned Size   = (ArgFlags & ISD::ParamFlags::ByValSize) >>
+      ISD::ParamFlags::ByValSizeOffs;
+  unsigned Offset = AllocateStack(Size, Align);
+
+  addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
+}
 
 /// MarkAllocated - Mark a register and all of its aliases as allocated.
 void CCState::MarkAllocated(unsigned Reg) {
@@ -99,4 +110,3 @@ void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) {
     }
   }
 }
-
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index afb681f9bd..df40972196 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3836,8 +3836,15 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       Flags |= ISD::ParamFlags::InReg;
     if (Attrs && Attrs->paramHasAttr(j, ParamAttr::StructRet))
       Flags |= ISD::ParamFlags::StructReturn;
-    if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal))
+    if (Attrs && Attrs->paramHasAttr(j, ParamAttr::ByVal)) {
       Flags |= ISD::ParamFlags::ByVal;
+      const PointerType *Ty = cast<PointerType>(I->getType());
+      const StructType *STy = cast<StructType>(Ty->getElementType());
+      unsigned StructAlign = Log2_32(getTargetData()->getABITypeAlignment(STy));
+      unsigned StructSize  = getTargetData()->getTypeSize(STy);
+      Flags |= (StructAlign << ISD::ParamFlags::ByValAlignOffs);
+      Flags |= (StructSize  << ISD::ParamFlags::ByValSizeOffs);
+    }
     if (Attrs && Attrs->paramHasAttr(j, ParamAttr::Nest))
       Flags |= ISD::ParamFlags::Nest;
     Flags |= (OriginalAlignment << ISD::ParamFlags::OrigAlignmentOffs);
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 3af393484e..184e355369 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1260,7 +1260,12 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
       int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
                                       VA.getLocMemOffset());
       SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
-      ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
+
+      unsigned Flags =  cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
+      if (Flags & ISD::ParamFlags::ByVal)
+        ArgValues.push_back(FIN);
+      else
+        ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
     }
   }
   
diff --git a/utils/TableGen/CallingConvEmitter.cpp b/utils/TableGen/CallingConvEmitter.cpp
index 2929aba820..5c88b5fc7a 100644
--- a/utils/TableGen/CallingConvEmitter.cpp
+++ b/utils/TableGen/CallingConvEmitter.cpp
@@ -130,7 +130,9 @@ void CallingConvEmitter::EmitAction(Record *Action,
         << IndentStr << "else\n"
         << IndentStr << IndentStr << "LocInfo = CCValAssign::AExt;\n";
     } else if (Action->isSubClassOf("CCStructAssign")) {
-      O << "assert(0 && \"Not Implemented\");\n";
+      O << IndentStr <<
+          "State.HandleStruct(ValNo, ValVT, LocVT, LocInfo, ArgFlags);\n";
+      O << IndentStr << "return false;\n";
     } else {
       Action->dump();
       throw "Unknown CCAction!";