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author | Johnny Chen <johnny.chen@apple.com> | 2010-03-26 18:32:20 +0000 |
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committer | Johnny Chen <johnny.chen@apple.com> | 2010-03-26 18:32:20 +0000 |
commit | 575c91cba78332bd9add0949e31a9c228c44cf00 (patch) | |
tree | f2a9bca917b1acc04e4b421239076eec7f5c0c2b | |
parent | 2c12cb47d95ff40f02951344ffee6bfd6ee6e900 (diff) |
Add N3RegFrm to represent "NEON 3 vector register format" instructions.
Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 1320bb4dca..3504d0add3 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -66,6 +66,7 @@ def NVCVTFrm : Format<34>; def NVDupLnFrm : Format<35>; def N2RegVShLFrm : Format<36>; def N2RegVShRFrm : Format<37>; +def N3RegFrm : Format<38>; // Misc flags. @@ -1606,7 +1607,7 @@ class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list<dag> pattern> - : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> { + : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; @@ -1620,7 +1621,7 @@ class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4, dag oops, dag iops, InstrItinClass itin, string opc, string asm, string cstr, list<dag> pattern> - : NDataXI<oops, iops, NEONFrm, itin, opc, asm, cstr, pattern> { + : NDataXI<oops, iops, N3RegFrm, itin, opc, asm, cstr, pattern> { let Inst{24} = op24; let Inst{23} = op23; let Inst{21-20} = op21_20; |