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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-01 21:54:09 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-08-01 21:54:09 +0000 |
| commit | 55244ceac400dfb170d4df81029ddec9f38ad7cc (patch) | |
| tree | 06f3f4b045360560a41091d32e7522df50337415 | |
| parent | aed890bee04cce1896a4230cd493774c9700f545 (diff) | |
Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise
the legalizer. This commit together with the two previous ones fixes
PR10495.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136654 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-256-cvt.ll | 7 |
3 files changed, 14 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c6dede979d..b00b00d047 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -966,6 +966,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); + setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 066f7c01a5..acd0c6b7a6 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1054,6 +1054,12 @@ def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src), def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)), (VCVTTPS2DQYrm addr:$src)>; +// Match fround for 128/256-bit conversions +def : Pat<(v4f32 (fround (v4f64 VR256:$src))), + (VCVTPD2PSYrr VR256:$src)>; +def : Pat<(v4f32 (fround (loadv4f64 addr:$src))), + (VCVTPD2PSYrm addr:$src)>; + //===----------------------------------------------------------------------===// // SSE 1 & 2 - Compare Instructions //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/X86/avx-256-cvt.ll b/test/CodeGen/X86/avx-256-cvt.ll index 8bf67568b6..d97327906c 100644 --- a/test/CodeGen/X86/avx-256-cvt.ll +++ b/test/CodeGen/X86/avx-256-cvt.ll @@ -12,3 +12,10 @@ define <8 x i32> @funcB(<8 x float> %a) nounwind { ret <8 x i32> %b } +; CHECK: vcvtpd2psy %ymm +; CHECK-NEXT: vcvtpd2psy %ymm +; CHECK-NEXT: vinsertf128 $1 +define <8 x float> @funcC(<8 x double> %b) nounwind { + %a = fptrunc <8 x double> %b to <8 x float> + ret <8 x float> %a +} |