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| author | Evan Cheng <evan.cheng@apple.com> | 2009-02-05 22:24:17 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-02-05 22:24:17 +0000 |
| commit | 54801f78b1ed0078a4c07cbb5472830335987f66 (patch) | |
| tree | 7f149d383f48785f1b8deeb4251e203a4824dfc2 | |
| parent | 3484c09e0da3c05c8a78946e090c7610208d937b (diff) | |
isAsCheapAsMove instructions can have register src operands. Check if they are really re-materializable.
This fixes sse.expandfft and sse.stepfft.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63890 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/X86/2009-02-05-CoalescerBug.ll | 12 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 28d249235d..f09eee64b2 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -558,6 +558,9 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, const TargetInstrDesc &TID = DefMI->getDesc(); if (!TID.isAsCheapAsAMove()) return false; + if (!DefMI->getDesc().isRematerializable() || + !tii_->isTriviallyReMaterializable(DefMI)) + return false; bool SawStore = false; if (!DefMI->isSafeToMove(tii_, SawStore)) return false; diff --git a/test/CodeGen/X86/2009-02-05-CoalescerBug.ll b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll new file mode 100644 index 0000000000..e57238a7b9 --- /dev/null +++ b/test/CodeGen/X86/2009-02-05-CoalescerBug.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss | count 2 +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movaps | count 4 + +define i1 @cfft2_bb12_bb12_2E_ce([2 x float]* %y, [2 x float]* %w, i32, [2 x float]* %x.pn59, i32 %smax190, i32 %j.1180, <4 x float> %wu.2179, <4 x float> %wr.2178, <4 x float>* %tmp89.out, <4 x float>* %tmp107.out, i32* %indvar.next218.out) nounwind { +newFuncRoot: + %tmp82 = insertelement <4 x float> %wr.2178, float 0.000000e+00, i32 0 ; <<4 x float>> [#uses=1] + %tmp85 = insertelement <4 x float> %tmp82, float 0.000000e+00, i32 1 ; <<4 x float>> [#uses=1] + %tmp87 = insertelement <4 x float> %tmp85, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1] + %tmp89 = insertelement <4 x float> %tmp87, float 0.000000e+00, i32 3 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp89, <4 x float>* %tmp89.out + ret i1 false +} |