Ensure that mov and not lea are used to stick the address into

the register.  While we're at it, make sure it's in the right one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 21 insertions, 10 deletions

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 81f5b19479..6d88454ba8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -8527,18 +8527,29 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
   // our load from the relocation, sticking it in either RDI (x86-64)
   // or EAX and doing an indirect call.  The return value will then
   // be in the normal return register.
-  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+  const X86InstrInfo *TII 
+    = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
   DebugLoc DL = MI->getDebugLoc();
   MachineFunction *F = BB->getParent();
   
+  assert(MI->getOperand(3).isGlobal() && "This should be a global");
+  
   if (Subtarget->is64Bit()) {
-    MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rr), X86::RDI)
-    .addReg(MI->getOperand(0).getReg());
+    MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rm), X86::RDI)
+    .addReg(X86::RIP)
+    .addImm(0).addReg(0)
+    .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 
+                      MI->getOperand(3).getTargetFlags())
+    .addReg(0);
     MIB = BuildMI(BB, DL, TII->get(X86::CALL64m));
     addDirectMem(MIB, X86::RDI).addReg(0);
   } else {
-    MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rr), X86::EAX)
-    .addReg(MI->getOperand(0).getReg());
+    MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX)
+    .addReg(TII->getGlobalBaseReg(F))
+    .addImm(0).addReg(0)
+    .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 
+                      MI->getOperand(3).getTargetFlags())
+    .addReg(0);
     MIB = BuildMI(BB, DL, TII->get(X86::CALL32m));
     addDirectMem(MIB, X86::EAX).addReg(0);
   }
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index f40092c9b7..e2d64ba6f5 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -66,7 +66,7 @@ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
 
 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
                                [tglobaltlsaddr], []>;
-
+                               
 //===----------------------------------------------------------------------===//
 // Pattern fragments.
 //
@@ -1717,9 +1717,9 @@ let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
     Uses = [RSP],
     usesCustomInserter = 1 in
-def TLSCall_64 : I<0, Pseudo, (outs), (ins GR64:$sym),
+def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
                   "# Fixme into a call",
-                  [(X86TLSCall GR64:$sym)]>,
+                  [(X86TLSCall addr:$sym)]>,
                   Requires<[In64BitMode]>;
 
 let AddedComplexity = 5, isCodeGenOnly = 1 in
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 36e493a7c1..d77fc4aca3 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3837,9 +3837,9 @@ let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
             XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
     Uses = [ESP],
     usesCustomInserter = 1 in
-def TLSCall_32 : I<0, Pseudo, (outs), (ins GR32:$sym),
+def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
                 "# Fixme into a call",
-                [(X86TLSCall GR32:$sym)]>,
+                [(X86TLSCall addr:$sym)]>,
                 Requires<[In32BitMode]>;
                 
 let AddedComplexity = 5, isCodeGenOnly = 1 in