diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-01-24 21:41:09 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-01-24 21:41:09 +0000 |
| commit | 5387f2e4f3b1982ee7236fa8db92f9c5152dc058 (patch) | |
| tree | e8866182446a43cca0fe6e626a3a0be31068d370 | |
| parent | f35307ceac57194094f207f0920fbd22231f5331 (diff) | |
64-bit sign extension in register instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 11 | ||||
| -rw-r--r-- | test/CodeGen/Mips/2008-07-16-SignExtInReg.ll | 12 |
3 files changed, 14 insertions, 13 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index fb1cea58fd..56d2b42f64 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -178,6 +178,10 @@ def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>; def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>; def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>; +/// Sign Ext In Register Instructions. +def SEB64 : SignExtInReg<0x10, "seb", i8, CPU64Regs>; +def SEH64 : SignExtInReg<0x18, "seh", i16, CPU64Regs>; + /// Count Leading def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>; def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 9aca566895..39007c6c71 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -616,10 +616,11 @@ class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: } // Sign Extend in Register. -class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>: - FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt), +class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, + RegisterClass RC>: + FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), !strconcat(instr_asm, "\t$rd, $rt"), - [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> { + [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { let rs = 0; let shamt = sa; let Predicates = [HasSEInReg]; @@ -889,8 +890,8 @@ def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; /// Sign Ext In Register Instructions. -def SEB : SignExtInReg<0x10, "seb", i8>; -def SEH : SignExtInReg<0x18, "seh", i16>; +def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; +def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; /// Count Leading def CLZ : CountLeading0<0x20, "clz", CPURegs>; diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll index e0c745f349..8479ad222d 100644 --- a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll +++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll @@ -1,20 +1,16 @@ -; DISABLED: llc < %s -march=mips -o %t -; DISABLED: grep seh %t | count 1 -; DISABLED: grep seb %t | count 1 -; RUN: false -; XFAIL: * - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-unknown-psp-elf" +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind { entry: +; CHECK: seb add i8 %sum, %e.0 ; <i8>:0 [#uses=1] ret i8 %0 } define signext i16 @B(i16 %e.0, i16 signext %sum) nounwind { entry: +; CHECK: seh add i16 %sum, %e.0 ; <i16>:0 [#uses=1] ret i16 %0 } |