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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-10-26 10:45:47 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-10-26 10:45:47 +0000 |
| commit | 505faa6b12dcfadf59323701239ba23cd7eda932 (patch) | |
| tree | 25ad34779c6bf770331b986bc45d28160d4498b3 | |
| parent | 15b337c28da771b8426fafad58f2e2f81ca4c64e (diff) | |
Change v64 datalayout in SPU.
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays,
we use array alignment for v64 too. This makes the
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.
This also makes an "unaligned store" test to be
aligned, with different (but functionally equivalent)
code generated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117360 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUSubtarget.h | 2 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/v2f32.ll | 3 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/v2i32.ll | 14 |
3 files changed, 16 insertions, 3 deletions
diff --git a/lib/Target/CellSPU/SPUSubtarget.h b/lib/Target/CellSPU/SPUSubtarget.h index 88201c653b..147163d52e 100644 --- a/lib/Target/CellSPU/SPUSubtarget.h +++ b/lib/Target/CellSPU/SPUSubtarget.h @@ -81,7 +81,7 @@ namespace llvm { /// properties of this subtarget. const char *getTargetDataString() const { return "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128" - "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:128:128-v128:128:128" + "-i16:16:128-i8:8:128-i1:8:128-a:0:128-v64:64:128-v128:128:128" "-s:128:128-n32:64"; } }; diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index b81c0cdbb2..efd0320310 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -62,8 +62,7 @@ define %vec @test_insert(){ } define void @test_unaligned_store() { -;CHECK: cdd $3, 8($3) -;CHECK: lqd +;CHECK: cdd ;CHECK: shufb ;CHECK: stqd %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1] diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll index 8cfc490e02..71d4aba633 100644 --- a/test/CodeGen/CellSPU/v2i32.ll +++ b/test/CodeGen/CellSPU/v2i32.ll @@ -61,3 +61,17 @@ define void @test_store( %vec %val, %vec* %ptr) store %vec %val, %vec* %ptr ret void } + +;Alignment of <2 x i32> is not *directly* defined in the ABI +;It probably is safe to interpret it as an array, thus having 8 byte +;alignment (according to ABI). This tests that the size of +;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the +;two arrays +define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr) +{ +; CHECK-NOT: ai $3, $3, 16 +; CHECK: ai $3, $3, 8 +; CHECK: bi $lr + %rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1 + ret <2 x i32>* %rv +} |