diff options
| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-19 19:57:37 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-19 19:57:37 +0000 |
| commit | 4fc8a5de44c2fc3ce82d5467bd96dfe25aa3a0e9 (patch) | |
| tree | 6896106d3b170a2ffc5fc709e13c948a05aa7f9a | |
| parent | 9e7e04823cb472ae8c36ce354365ba76ba1bcb36 (diff) | |
Add support for additional in-reg vbroadcast patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157127 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx2-vbroadcast.ll | 37 |
2 files changed, 46 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 439cd4f862..203c8733aa 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -5026,12 +5026,18 @@ X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const { } } + bool IsLoad = ISD::isNormalLoad(Ld.getNode()); + unsigned ScalarSize = Ld.getValueType().getSizeInBits(); + + // Handle AVX2 in-register broadcasts. + if (!IsLoad && Subtarget->hasAVX2() && + (ScalarSize == 32 || (Is256 && ScalarSize == 64))) + return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); + // The scalar source must be a normal load. - if (!ISD::isNormalLoad(Ld.getNode())) + if (!IsLoad) return SDValue(); - unsigned ScalarSize = Ld.getValueType().getSizeInBits(); - if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld); diff --git a/test/CodeGen/X86/avx2-vbroadcast.ll b/test/CodeGen/X86/avx2-vbroadcast.ll index 6eba694bd4..46b41fa953 100644 --- a/test/CodeGen/X86/avx2-vbroadcast.ll +++ b/test/CodeGen/X86/avx2-vbroadcast.ll @@ -222,3 +222,40 @@ footer349VF: ret: ret void } + +; CHECK: _inreg0 +; CHECK: broadcastss +; CHECK: ret +define <8 x i32> @_inreg0(i32 %scalar) nounwind uwtable readnone ssp { + %in = insertelement <8 x i32> undef, i32 %scalar, i32 0 + %wide = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer + ret <8 x i32> %wide +} + +; CHECK: _inreg1 +; CHECK: broadcastss +; CHECK: ret +define <8 x float> @_inreg1(float %scalar) nounwind uwtable readnone ssp { + %in = insertelement <8 x float> undef, float %scalar, i32 0 + %wide = shufflevector <8 x float> %in, <8 x float> undef, <8 x i32> zeroinitializer + ret <8 x float> %wide +} + +; CHECK: _inreg2 +; CHECK: broadcastss +; CHECK: ret +define <4 x float> @_inreg2(float %scalar) nounwind uwtable readnone ssp { + %in = insertelement <4 x float> undef, float %scalar, i32 0 + %wide = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> zeroinitializer + ret <4 x float> %wide +} + +; CHECK: _inreg3 +; CHECK: broadcastsd +; CHECK: ret +define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp { + %in = insertelement <4 x double> undef, double %scalar, i32 0 + %wide = shufflevector <4 x double> %in, <4 x double> undef, <4 x i32> zeroinitializer + ret <4 x double> %wide +} + |