diff options
author | Brian Gaeke <gaeke@uiuc.edu> | 2004-11-18 00:25:20 +0000 |
---|---|---|
committer | Brian Gaeke <gaeke@uiuc.edu> | 2004-11-18 00:25:20 +0000 |
commit | 4b92ed6d584aaa34eab7a3ef60d277617adb9aca (patch) | |
tree | cbf2173ba98dde6b9a96b35ea698505ab6e69846 | |
parent | c935cf111cfc80cac641e3b0ba463afd49f484b0 (diff) |
Allocate fewer registers and tighten up alignment restrictions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17929 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 15 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcTargetMachine.cpp | 2 | ||||
-rw-r--r-- | lib/Target/SparcV8/SparcV8RegisterInfo.td | 15 | ||||
-rw-r--r-- | lib/Target/SparcV8/SparcV8TargetMachine.cpp | 2 |
4 files changed, 24 insertions, 10 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index b3d202bf26..6e0806a3a9 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -25,13 +25,20 @@ include "../SparcRegisterInfo.td" // def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, - G1, G2, G3, G4, G5, G6, G7, + G1, O0, O1, O2, O3, O4, O5, O7, - // Non-allocatable regs - O6, I6, I7, G0]> { + // Non-allocatable regs: + G2, G3, G4, // FIXME: OK for use only in + // applications, not libraries. + O6, // stack ptr + I6, // frame ptr + I7, // return address + G0, // constant zero + G5, G6, G7 // reserved for kernel + ]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { - return end()-4; // Don't allocate special registers + return end()-10; // Don't allocate special registers } }]; } diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index a6b69d6263..604f683499 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -31,7 +31,7 @@ namespace { /// SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL) - : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8), + : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8, 4, 4, 4, 4), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { } diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td index b3d202bf26..6e0806a3a9 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -25,13 +25,20 @@ include "../SparcRegisterInfo.td" // def IntRegs : RegisterClass<i32, 32, [L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, - G1, G2, G3, G4, G5, G6, G7, + G1, O0, O1, O2, O3, O4, O5, O7, - // Non-allocatable regs - O6, I6, I7, G0]> { + // Non-allocatable regs: + G2, G3, G4, // FIXME: OK for use only in + // applications, not libraries. + O6, // stack ptr + I6, // frame ptr + I7, // return address + G0, // constant zero + G5, G6, G7 // reserved for kernel + ]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { - return end()-4; // Don't allocate special registers + return end()-10; // Don't allocate special registers } }]; } diff --git a/lib/Target/SparcV8/SparcV8TargetMachine.cpp b/lib/Target/SparcV8/SparcV8TargetMachine.cpp index a6b69d6263..604f683499 100644 --- a/lib/Target/SparcV8/SparcV8TargetMachine.cpp +++ b/lib/Target/SparcV8/SparcV8TargetMachine.cpp @@ -31,7 +31,7 @@ namespace { /// SparcV8TargetMachine::SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL) - : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8), + : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8, 4, 4, 4, 4), FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) { } |