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| author | Evan Cheng <evan.cheng@apple.com> | 2008-04-25 20:13:28 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-04-25 20:13:28 +0000 |
| commit | 44c0fd17e11dd3a6cda81632cac5b06fb1618d93 (patch) | |
| tree | d61e7d8d0088bef42eda923e55c75df2e05e2668 | |
| parent | 082948df9bff94a21da4873b9b9e612652055c19 (diff) | |
Extract the lower 64-bit if a MMX value is passed in a XMM register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50292 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 21178ef78d..8d37663676 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1248,9 +1248,15 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue); // Handle MMX values passed in GPRs. - if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass && - MVT::getSizeInBits(RegVT) == 64) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); + if (Is64Bit && RegVT != VA.getLocVT()) { + if (MVT::getSizeInBits(RegVT) == 64 && RC == X86::GR64RegisterClass) + ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); + else if (RC == X86::VR128RegisterClass) { + ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue, + DAG.getConstant(0, MVT::i64)); + ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue); + } + } ArgValues.push_back(ArgValue); } else { |