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authorVikram S. Adve <vadve@cs.uiuc.edu>2001-11-08 05:22:15 +0000
committerVikram S. Adve <vadve@cs.uiuc.edu>2001-11-08 05:22:15 +0000
commit44508e333cc1d36e699aa330d84312d1c8fc655a (patch)
tree9da4a8db723c6c74fb40bee0386be4e026edeae5
parente64574ce7198dc0967caf811dd295fd8df91409c (diff)
Add method CreateCodeToCopyIntToFloat.
Include handle to TargetMachine in each Machine...Info object. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1200 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/Target/MachineInstrInfo.h19
-rw-r--r--include/llvm/Target/TargetInstrInfo.h19
2 files changed, 36 insertions, 2 deletions
diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h
index 696738a151..abe6a81362 100644
--- a/include/llvm/Target/MachineInstrInfo.h
+++ b/include/llvm/Target/MachineInstrInfo.h
@@ -72,13 +72,17 @@ struct MachineInstrDescriptor {
class MachineInstrInfo : public NonCopyableV {
+public:
+ const TargetMachine& target;
+
protected:
const MachineInstrDescriptor* desc; // raw array to allow static init'n
unsigned int descSize; // number of entries in the desc array
unsigned int numRealOpCodes; // number of non-dummy op codes
public:
- MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
+ MachineInstrInfo(const TargetMachine& tgt,
+ const MachineInstrDescriptor *desc, unsigned descSize,
unsigned numRealOpCodes);
virtual ~MachineInstrInfo();
@@ -231,6 +235,19 @@ public:
Instruction* dest,
vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& temps) const =0;
+
+ // Create an instruction sequence to copy an integer value `val' from an
+ // integer to a floating point register `dest'. val must be an integral
+ // type. dest must be a Float or Double.
+ // The generated instructions are returned in `minstrVec'.
+ // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
+ //
+ virtual void CreateCodeToCopyIntToFloat(Method* method,
+ Value* val,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec,
+ vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const = 0;
};
#endif
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 696738a151..abe6a81362 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -72,13 +72,17 @@ struct MachineInstrDescriptor {
class MachineInstrInfo : public NonCopyableV {
+public:
+ const TargetMachine& target;
+
protected:
const MachineInstrDescriptor* desc; // raw array to allow static init'n
unsigned int descSize; // number of entries in the desc array
unsigned int numRealOpCodes; // number of non-dummy op codes
public:
- MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
+ MachineInstrInfo(const TargetMachine& tgt,
+ const MachineInstrDescriptor *desc, unsigned descSize,
unsigned numRealOpCodes);
virtual ~MachineInstrInfo();
@@ -231,6 +235,19 @@ public:
Instruction* dest,
vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& temps) const =0;
+
+ // Create an instruction sequence to copy an integer value `val' from an
+ // integer to a floating point register `dest'. val must be an integral
+ // type. dest must be a Float or Double.
+ // The generated instructions are returned in `minstrVec'.
+ // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
+ //
+ virtual void CreateCodeToCopyIntToFloat(Method* method,
+ Value* val,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec,
+ vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const = 0;
};
#endif