Translate llvm target registers to dwarf register numbers properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 5 insertions, 5 deletions

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index f5c6dd67f5..fee062f84c 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -362,7 +362,7 @@ void AlphaRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? Alpha::R15 : Alpha::R30) - Alpha::R0,
+  ML.set(getDwarfRegNum(FP ? Alpha::R15 : Alpha::R30),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index f6d9941f8e..c8d6f0fdf5 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -337,7 +337,7 @@ void IA64RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? IA64::r5 : IA64::r12) - IA64::r0,
+  ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 6b281bd2d8..984d5e23fd 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -454,7 +454,7 @@ void PPCRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set((FP ? PPC::R31 : PPC::R1) - PPC::R0,
+  ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 21a0cd85d8..cbeb87fa54 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -207,7 +207,7 @@ void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
   
   // FIXME - Needs to handle register variables.
   // FIXME - Faking that llvm number is same as gcc numbering.
-  ML.set(SP::G1 - SP::G0,
+  ML.set(getDwarfRegNum(SP::G1),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }
 
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 88aa0155d1..99e36eb369 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -693,7 +693,7 @@ void X86RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
   
   // FIXME - Needs to handle register variables.
   // FIXME - Hardcoding gcc numbering.
-  ML.set(FP ? 6 : 7,
+  ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
          MFI->getObjectOffset(Index) + MFI->getStackSize());
 }