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| author | Bill Wendling <isanbard@gmail.com> | 2010-08-11 00:23:00 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-08-11 00:23:00 +0000 |
| commit | 38ae997e63e3e1bb2c8679e01ea74cf8fd0be893 (patch) | |
| tree | 8049f1a097d7a996b1d9cf4c694c5c2cdebbb88a | |
| parent | 0cce3dd3267e8416a34ef59ac72351dc9e1e30eb (diff) | |
Handle ARM compares as well as converting for ARM adds, subs, and thumb2's adds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110762 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 5881a121a9..7e166d5273 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1358,6 +1358,8 @@ bool ARMBaseInstrInfo:: AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const { switch (MI->getOpcode()) { default: break; + case ARM::CMPri: + case ARM::CMPzri: case ARM::t2CMPri: case ARM::t2CMPzri: SrcReg = MI->getOperand(0).getReg(); @@ -1398,6 +1400,9 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { // Set the "zero" bit in CPSR. switch (MI->getOpcode()) { default: break; + case ARM::ADDri: + case ARM::SUBri: + case ARM::t2ADDri: case ARM::t2SUBri: { MI->RemoveOperand(5); MachineInstrBuilder MB(MI); |