diff options
| author | Benjamin Kramer <benny.kra@googlemail.com> | 2012-11-28 20:55:10 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2012-11-28 20:55:10 +0000 |
| commit | 350c00843bad22c5391e33e9e39a78d5d0983c8c (patch) | |
| tree | 1b85e673c4414ebeaed6c45c820483fb3ecf4e78 | |
| parent | 1ead68d769f27f6d68d4aaeffe4199fa2cacbc95 (diff) | |
ARM: Implement CanLowerReturn so large vectors get expanded into sret.
Fixes 14337.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 6 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ret_sret_vector.ll | 12 |
3 files changed, 29 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index bd470eb4bb..b2af378977 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1882,6 +1882,17 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, return true; } +bool +ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const { + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context); + return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true, + isVarArg)); +} + SDValue ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 8bf803edee..9cbf866f9b 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -495,6 +495,12 @@ namespace llvm { const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; + + virtual bool CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const; + virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, diff --git a/test/CodeGen/ARM/ret_sret_vector.ll b/test/CodeGen/ARM/ret_sret_vector.ll new file mode 100644 index 0000000000..9bb3519555 --- /dev/null +++ b/test/CodeGen/ARM/ret_sret_vector.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "thumbv7-apple-ios3.0.0" + +define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) { + %foo = fadd <4 x double> %a, %b + ret <4 x double> %foo +; CHECK: PR14337: +; CHECK: vst1.64 +; CHECK: vst1.64 +} |