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authorEric Christopher <echristo@apple.com>2011-06-27 20:31:01 +0000
committerEric Christopher <echristo@apple.com>2011-06-27 20:31:01 +0000
commit34720e193f55458c13de017f628f636aca9d768e (patch)
treef233f6d492a7133ed3d3af1bc7ba880a4851b9ae
parent0d06bb954881dc7ff0e2333d5a3e249b7bb304d0 (diff)
Allow lr in the register options here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--test/CodeGen/ARM/arm-modifier.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index 0a7bb6cd21..396de37aef 100644
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -46,9 +46,9 @@ ret void
define void @f3() nounwind {
entry:
; CHECK: f3
-; CHECK: stm r{{[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
-; CHECK: adds lr, [[REG1]]
-; CHECK: ldm r{{[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
+; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
+; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
+; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
%tmp = load i64* @f3_var, align 4
%tmp1 = load i64* @f3_var2, align 4
%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind