diff options
| author | Owen Anderson <resistor@mac.com> | 2011-09-23 21:07:25 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-09-23 21:07:25 +0000 |
| commit | 31d485ec9a2afcf83c5354061568b4280d61b574 (patch) | |
| tree | 0843fe3196bfb6bfdcfdde8b984edef4336f61fd | |
| parent | df0caeb6eca5c3424b4ccef5f489708392450982 (diff) | |
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb2.txt | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6be49169b4..a775cf61b5 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2660,7 +2660,7 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, break; default: { unsigned Rt = fieldFromInstruction32(Insn, 12, 4); - if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) + if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; } } diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index 19351e01f5..2af27b4f34 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -649,14 +649,14 @@ # CHECK: ldrh.w r5, [r6, #33] # CHECK: ldrh.w r5, [r6, #257] # CHECK: ldrh.w lr, [r7, #257] -# CHECK: ldrh.w sp, [pc, #-21] +# CHECK: ldrh.w r0, [pc, #-21] 0x35 0xf8 0x04 0x5c 0x35 0x8c 0xb6 0xf8 0x21 0x50 0xb6 0xf8 0x01 0x51 0xb7 0xf8 0x01 0xe1 -0x3f 0xf8 0x15 0xd0 +0x3f 0xf8 0x15 0x00 #------------------------------------------------------------------------------ |