diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-11 23:22:18 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-11 23:22:18 +0000 |
| commit | 3011a33a63b055fc3c0bba51728e13c8b0f1c20e (patch) | |
| tree | 3b17a228fc70eb5a8793ddff8b302294bad649f9 | |
| parent | aefd36bdda0dac496b8acabb25f0de29b370ebca (diff) | |
Do not replace operands of pseudo instructions with register $zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Mips/MipsISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/Mips/atomic.ll | 16 |
2 files changed, 18 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 6e5bad7f15..027c171eff 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -213,7 +213,8 @@ bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI, MachineInstr *MI = MO.getParent(); // Do not replace if it is a phi's operand or is tied to def operand. - if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo())) + if (MI->isPHI() || MI->isRegTiedToDefOperand(U.getOperandNo()) || + MI->isPseudo()) continue; MO.setReg(ZeroReg); diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index a4763b130d..e181610ec3 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -242,3 +242,19 @@ entry: ; CHECK: sync 0 } +; make sure that this assertion in +; TwoAddressInstructionPass::TryInstructionTransform does not fail: +; +; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) && +; +; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an +; operand of an atomic instruction with register $zero. +@a = external global i32 + +define i32 @zeroreg() nounwind { +entry: + %0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst + %1 = icmp eq i32 %0, 1 + %conv = zext i1 %1 to i32 + ret i32 %conv +} |