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| author | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:13:09 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-08-21 20:13:09 +0000 |
| commit | 2b0e300342cee213d3df41bf72d84316651805bb (patch) | |
| tree | 5dab337a41986f4a58ec6accf1ffeb26f5e8a1aa | |
| parent | 0e362770d03a10ed49f75b75aa5673bc9026e3da (diff) | |
Convert regclass alignment from bytes to bites
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15972 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SparcV9/SparcV9RegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/SparcV9/SparcV9RegisterInfo.td b/lib/Target/SparcV9/SparcV9RegisterInfo.td index b59edaea20..bea8f033db 100644 --- a/lib/Target/SparcV9/SparcV9RegisterInfo.td +++ b/lib/Target/SparcV9/SparcV9RegisterInfo.td @@ -35,7 +35,7 @@ let Namespace = "SparcV9" in { // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7, +def IntRegs : RegisterClass<i64, 64, [G0, G1, G2, G3, G4, G5, G6, G7, O0, O1, O2, O3, O4, O5, O6, O7, L0, L1, L2, L3, L4, L5, L6, L7, I0, I1, I2, I3, I4, I5, I6, I7]>; |