diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-02-01 20:35:57 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-02-01 20:35:57 +0000 |
| commit | 2a8fc2341121648272edc911479ca85c6c1186e4 (patch) | |
| tree | b598d0edaff328d3161afe50557db1df0a52f85b | |
| parent | 2f401633238248da6b1abea0fe0b942358197b9a (diff) | |
Correct stack stuff for FP
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19973 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 055bf14d91..bd38fd4080 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -49,8 +49,12 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned SrcReg, int FrameIdx) const { //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); - BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - // assert(0 && "TODO"); + if (getClass(SrcReg) == Alpha::FPRCRegisterClass) + BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + else if (getClass(SrcReg) == Alpha::GPRCRegisterClass) + BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + else + abort(); } void @@ -58,9 +62,12 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx) const{ //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; - //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg); - BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - // assert(0 && "TODO"); + if (getClass(DestReg) == Alpha::FPRCRegisterClass) + BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + else if (getClass(DestReg) == Alpha::GPRCRegisterClass) + BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + else + abort(); } void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, |