diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-05-10 08:13:49 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-05-10 08:13:49 +0000 |
| commit | 26c4cf4c6fedb3439d4a9f8f7375ff1c61e0acd5 (patch) | |
| tree | 8322e0b39ca3079f36cae9837ba872fdb53a757d | |
| parent | faa95763ebb081769bf6ac35e170394c9d477813 (diff) | |
Fix encoding of 'sf' and 'sfh' instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103399 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 6 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/sub_ops.ll | 26 |
2 files changed, 29 insertions, 3 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index 6d1f87dd30..a7fb14c26a 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -655,7 +655,7 @@ def SFHvec: def SFHr16: RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB), "sfh\t$rT, $rA, $rB", IntegerOp, - [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>; + [(set R16C:$rT, (sub R16C:$rB, R16C:$rA))]>; def SFHIvec: RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), @@ -670,11 +670,11 @@ def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val), def SFvec : RRForm<0b00000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), "sf\t$rT, $rA, $rB", IntegerOp, - [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>; + [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rB), (v4i32 VECREG:$rA)))]>; def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB), "sf\t$rT, $rA, $rB", IntegerOp, - [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>; + [(set R32C:$rT, (sub R32C:$rB, R32C:$rA))]>; def SFIvec: RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val), diff --git a/test/CodeGen/CellSPU/sub_ops.ll b/test/CodeGen/CellSPU/sub_ops.ll new file mode 100644 index 0000000000..f0c40d37ce --- /dev/null +++ b/test/CodeGen/CellSPU/sub_ops.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=cellspu | FileCheck %s + +define i32 @subword( i32 %param1, i32 %param2) { +; Check ordering of registers ret=param1-param2 -> rt=rb-ra +; CHECK-NOT: sf $3, $3, $4 +; CHECK: sf $3, $4, $3 + %1 = sub i32 %param1, %param2 + ret i32 %1 +} + +define i16 @subhword( i16 %param1, i16 %param2) { +; Check ordering of registers ret=param1-param2 -> rt=rb-ra +; CHECK-NOT: sfh $3, $3, $4 +; CHECK: sfh $3, $4, $3 + %1 = sub i16 %param1, %param2 + ret i16 %1 +} + +define float @subfloat( float %param1, float %param2) { +; Check ordering of registers ret=param1-param2 -> rt=ra-rb +; (yes this is reverse of i32 instruction) +; CHECK-NOT: fs $3, $4, $3 +; CHECK: fs $3, $3, $4 + %1 = fsub float %param1, %param2 + ret float %1 +} |