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| author | Jim Grosbach <grosbach@apple.com> | 2010-04-22 18:28:43 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-04-22 18:28:43 +0000 |
| commit | 269e0fed84dba9f1ddb0b08730857ac9582b2cca (patch) | |
| tree | 8b124f773f2490aa85f6730ecd1eaff39183ea4d | |
| parent | cb28286b7b2957a06250b50e21348f297668b2b8 (diff) | |
Update ARM frame index scavenging description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102101 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | docs/ReleaseNotes.html | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index d36b0c2db3..c95f0b8d5c 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -737,8 +737,11 @@ href="http://blog.llvm.org/2010/04/arm-advanced-simd-neon-intrinsics-and.html"> helpful information if migrating code from GCC to LLVM-GCC.</li> <li>The ARM and Thumb code generators now use register scavenging for stack - object address materialization.(FIXME: WHAT BENEFIT DOES THIS PROVIDE?)</li> - + object address materialization. This allows the use of R3 as a general + purpose register in Thumb1 code, as it was previous reserved for use in + stack address materialization. Secondly, sequential uses of the same + value will now re-use the materialized constant.</li> + <li>The ARM backend now has good support for ARMv4 targets and has been tested on StrongARM hardware. Previously, LLVM only supported ARMv4T and newer chips.</li> |