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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-22 18:04:48 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-22 18:04:48 +0000 |
| commit | 248e6c328c06afc2a6af6b95a1a8a41c1b53055c (patch) | |
| tree | 22589a9471466e74cfd7724cb674b6c0ec2bddd0 | |
| parent | 0fdf6ccf17479a4fc383a1c54eb7dc816c0b5838 (diff) | |
ARM encoding and assembly parsing tests.
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 00087f3a66..42a60a463f 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1314,6 +1314,53 @@ _func: @------------------------------------------------------------------------------ +@ SEV +@------------------------------------------------------------------------------ + sev + seveq + +@ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3] +@ CHECK: seveq @ encoding: [0x04,0xf0,0x20,0x03] + +@------------------------------------------------------------------------------ +@ SHADD16/SHADD8 +@------------------------------------------------------------------------------ + shadd16 r4, r8, r2 + shadd16gt r4, r8, r2 + shadd8 r4, r8, r2 + shadd8gt r4, r8, r2 + +@ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6] +@ CHECK: shadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xc6] +@ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6] +@ CHECK: shadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shasx r4, r8, r2 + shasxgt r4, r8, r2 + +@ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHSUB16/SHSUB8 +@------------------------------------------------------------------------------ + shsub16 r4, r8, r2 + shsub16gt r4, r8, r2 + shsub8 r4, r8, r2 + shsub8gt r4, r8, r2 + +@ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6] +@ CHECK: shsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xc6] +@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6] +@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} |