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authorJim Grosbach <grosbach@apple.com>2011-12-06 05:28:00 +0000
committerJim Grosbach <grosbach@apple.com>2011-12-06 05:28:00 +0000
commit23261af193e462b73257445053f9f6515e60e8c9 (patch)
tree27eea4c56a8adcb778fe3db8b08263f5bd29ae59
parentcf9814ddd277dfcbb4ec5727e2cb510b8a451e04 (diff)
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td2
-rw-r--r--test/MC/ARM/basic-arm-instructions.s1
2 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 0b13598128..2639b6ff79 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -5067,4 +5067,4 @@ def : ARMInstAlias<"ror${s}${p} $Rn, $Rm",
// 'mul' instruction can be specified with only two operands.
def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
- (MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
+ (MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p, cc_out:$s)>;
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 133967b06b..2d8fbe173d 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1013,7 +1013,6 @@ Lforward:
@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0]
@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0]
@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0]
-@ CHECK: mul r11, r11, r5 @ encoding: [0x9b,0x05,0x0b,0xe0]
@------------------------------------------------------------------------------