diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-08-26 00:23:59 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-08-26 00:23:59 +0000 |
| commit | 23004e5f21716671401e95e3be91d87dc7d4d68b (patch) | |
| tree | beec08e5b61eb93d1df2c0f74dc9ae67486d0789 | |
| parent | 07dffd6af673c73352150583150b242a93694f00 (diff) | |
Add support for targets that want to custom expand select_cc in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23071 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 30 |
1 files changed, 24 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 283b46ec10..612e3e14aa 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1113,12 +1113,30 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp4 = LegalizeOp(Node->getOperand(3)); // False if (isTypeLegal(Node->getOperand(0).getValueType())) { - Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS - Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS - if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || - Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { - Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, - Tmp3, Tmp4, Node->getOperand(4)); + // Everything is legal, see if we should expand this op or something. + switch (TLI.getOperationAction(ISD::SELECT_CC, + Node->getOperand(0).getValueType())) { + default: assert(0 && "This action is not supported yet!"); + case TargetLowering::Custom: { + SDOperand Tmp = + TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), + Node->getOperand(0), + Node->getOperand(1), Tmp3, Tmp4, + Node->getOperand(5)), DAG); + if (Tmp.Val) { + Result = LegalizeOp(Tmp); + break; + } + } // FALLTHROUGH if the target can't lower this operation after all. + case TargetLowering::Legal: + Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS + Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS + if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || + Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { + Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, + Tmp3, Tmp4, Node->getOperand(4)); + } + break; } break; } else { |