diff options
| author | Jim Grosbach <grosbach@apple.com> | 2010-12-08 23:24:29 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-12-08 23:24:29 +0000 |
| commit | 20e0fa698d734f5c1b2c96ff5b266e393c82c0b9 (patch) | |
| tree | 0f4d338f1fe8c0971400a2f2582463c1e4d03fc7 | |
| parent | 0062db8b4f388308f8838805f160259a48a2882e (diff) | |
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121314 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 28 |
1 files changed, 9 insertions, 19 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 597ef72204..b2b32a9c7b 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -285,9 +285,13 @@ class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, : T2I<oops, iops, itin, opc, asm, pattern> { bits<4> Rd; bits<4> Rn; + bits<12> imm; let Inst{11-8} = Rd; - let Inst{3-0} = Rn; + let Inst{19-16} = Rn; + let Inst{26} = imm{11}; + let Inst{14-12} = imm{10-8}; + let Inst{7-0} = imm{7-0}; } class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, @@ -1159,18 +1163,12 @@ def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm), let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; } -def t2ADDrSPi12 : T2I<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm), - IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> { - bits<4> Rd; - bits<12> imm; +def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), + IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { let Inst{31-27} = 0b11110; - let Inst{26} = imm{11}; let Inst{25-20} = 0b100000; let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; - let Inst{14-12} = imm{10-8}; - let Inst{11-8} = Rd; - let Inst{7-0} = imm{7-0}; } // ADD r, sp, so_reg @@ -1180,7 +1178,6 @@ def t2ADDrSPs : T2sTwoRegShiftedReg< let Inst{31-27} = 0b11101; let Inst{26-25} = 0b01; let Inst{24-21} = 0b1000; - let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; } @@ -1193,18 +1190,11 @@ def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm), let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; } -def t2SUBrSPi12 : T2I<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm), - IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> { - bits<4> Rd; - bits<12> imm; +def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), + IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> { let Inst{31-27} = 0b11110; - let Inst{26} = imm{11}; let Inst{25-20} = 0b101010; - let Inst{19-16} = 0b1101; // Rn = sp let Inst{15} = 0; - let Inst{14-12} = imm{10-8}; - let Inst{11-8} = Rd; - let Inst{7-0} = imm{7-0}; } // SUB r, sp, so_reg |