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| author | Bob Wilson <bob.wilson@apple.com> | 2010-08-13 23:24:25 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-08-13 23:24:25 +0000 |
| commit | 20d8e4e7aa5645450f3eaedd9f9dbb70423f8ccc (patch) | |
| tree | eb3d45b1ed7775c7ed08dfc4eda03ad9210913b9 | |
| parent | 0a2b2a1497a77f1db281d4dc9f21d01fe48f6ec6 (diff) | |
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 23 | ||||
| -rw-r--r-- | test/MC/Disassembler/thumb-tests.txt | 4 |
2 files changed, 22 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 3165af65a3..16b7cb41f3 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -259,9 +259,9 @@ multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode, T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">; /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are -/// reversed. It doesn't define the 'rr' form since it's handled by its -/// T2I_bin_irs counterpart. -multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> { +/// reversed. The 'rr' form is only defined for the disassembler; for codegen +/// it is equivalent to the T2I_bin_irs counterpart. +multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { // shifted imm def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, opc, ".w\t$dst, $rhs, $lhs", @@ -272,6 +272,18 @@ multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> { let Inst{20} = ?; // The S bit. let Inst{15} = 0; } + // register + def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, + opc, "\t$dst, $rhs, $lhs", + [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { + let Inst{31-27} = 0b11101; + let Inst{26-25} = 0b01; + let Inst{24-21} = opcod; + let Inst{20} = ?; // The S bit. + let Inst{14-12} = 0b000; // imm3 + let Inst{7-6} = 0b00; // imm2 + let Inst{5-4} = 0b00; // type + } // shifted register def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, opc, "\t$dst, $rhs, $lhs", @@ -461,7 +473,8 @@ multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, } } -/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. +/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register +/// version is not needed since this is only for codegen. let Defs = [CPSR] in { multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { // shifted imm @@ -1387,7 +1400,7 @@ defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc", BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>; // RSB -defm t2RSB : T2I_rbin_is <0b1110, "rsb", +defm t2RSB : T2I_rbin_irs <0b1110, "rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; diff --git a/test/MC/Disassembler/thumb-tests.txt b/test/MC/Disassembler/thumb-tests.txt index 5d376000d6..4c690fb4d8 100644 --- a/test/MC/Disassembler/thumb-tests.txt +++ b/test/MC/Disassembler/thumb-tests.txt @@ -51,6 +51,10 @@ # CHECK: rsbs r0, r0, #0 0x40 0x42 +# CHECK-NOT: rsb r0, r2, r0, lsl #0 +# CHECK: rsb r0, r2, r0 +0xc2 0xeb 0x00 0x00 + # CHECK-NOT: ssat r0, #17, r12, lsl #0 # CHECK: ssat r0, #17, r12 0x0c 0xf3 0x10 0x00 |