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authorAndrew Lenharth <andrewl@lenharth.org>2005-04-14 17:34:20 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-04-14 17:34:20 +0000
commit1e0d9bda6214e8aaf3d6edd301255f5552242f12 (patch)
treee60bfe37fcb3332c43ea4a7dc10325de4a03fade
parent3ae1829fe5fa2523437e7f37f085010af37c475e (diff)
fix calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21303 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/Alpha/AlphaISelPattern.cpp1
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.td2
2 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 18cc35a356..d8459815fd 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1418,6 +1418,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal());
} else {
//use PC relative branch call
+ AlphaLowering.restoreGP(BB);
BuildMI(BB, Alpha::BSR, 1, Alpha::R26).addGlobalAddress(GASD->getGlobal(),true);
}
}
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 72f21f0bf9..e341e858cb 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -330,7 +330,7 @@ let isCall = 1,
R20, R21, R22, R23, R24, R25, R27, R28, R29,
F0, F1,
F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
- F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30] in {
+ F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
def JSR : MForm< 0x1A, (ops GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr $RD,($RS),$DISP">; //Jump to subroutine
def BSR : BForm<0x34, (ops GPRC:$RD, s21imm:$DISP), "bsr $RD,$DISP">; //Branch to subroutine
}