diff options
| author | Dan Gohman <gohman@apple.com> | 2008-04-28 23:26:22 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-04-28 23:26:22 +0000 |
| commit | 1d7153976c04723127bf6269b33a8ba81ae874d5 (patch) | |
| tree | ac112bee6fd9ee00528c3f754603a41e538cfef9 | |
| parent | 9d32f2aacbf3dd167cfde682882a842c34016fdf (diff) | |
Update and_ops.ll according to the recent dagcombiner changes.
Add a new test, and_ops_more.ll, which is XFAIL'd, to
record the parts of and_ops.ll that were affected by this
change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | test/CodeGen/CellSPU/and_ops.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/CellSPU/and_ops_more.ll | 26 |
2 files changed, 28 insertions, 2 deletions
diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index 46396ebb1f..a18b6f8d05 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep and %t1.s | count 232 +; RUN: grep and %t1.s | count 234 ; RUN: grep andc %t1.s | count 85 -; RUN: grep andi %t1.s | count 36 +; RUN: grep andi %t1.s | count 37 ; RUN: grep andhi %t1.s | count 30 ; RUN: grep andbi %t1.s | count 4 diff --git a/test/CodeGen/CellSPU/and_ops_more.ll b/test/CodeGen/CellSPU/and_ops_more.ll new file mode 100644 index 0000000000..3c9342a154 --- /dev/null +++ b/test/CodeGen/CellSPU/and_ops_more.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s +; RUN: grep and %t1.s | count 10 +; RUN: not grep andc %t1.s +; RUN: not grep andi %t1.s +; RUN: grep andhi %t1.s | count 5 +; RUN: grep andbi %t1.s | count 1 +; XFAIL: * + +; This testcase is derived from test/CodeGen/CellSPU/and_ops.ll and +; records the changes due to r50358. The and_sext8 function appears +; to be improved by this change, while the andhi_i16 function appears +; to be pessimized. + +target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" +target triple = "spu" + +define i16 @andhi_i16(i16 signext %in) signext { + %tmp38 = and i16 %in, 37 ; <i16> [#uses=1] + ret i16 %tmp38 +} + +define i8 @and_sext8(i8 signext %in) signext { + ; ANDBI generated + %tmp38 = and i8 %in, 37 + ret i8 %tmp38 +} |