diff options
| author | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 08:08:22 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2009-08-28 08:08:22 +0000 |
| commit | 19bb87d0f80f3e6eed38a9fa267bf2b0474aeaab (patch) | |
| tree | b2771de1b93e7d0d9c88465bee22d779dbaada9b | |
| parent | 8c3eaf46a1fb69004723ce78aaa82965d6474175 (diff) | |
Fix -Asserts warning, round two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80354 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index bc485daf6e..1c41073077 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1057,12 +1057,11 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (Done) return; - const TargetInstrDesc &Desc = MI.getDesc(); - // If we get here, the immediate doesn't fit into the instruction. We folded // as much as possible above, handle the rest, providing a register that is // SP+LargeImm. - assert((Offset || (Desc.TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && + assert((Offset || + (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && "This code isn't needed if offset already handled!"); // Insert a set of r12 with the full address: r12 = sp + offset |