diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-17 13:13:23 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-17 13:13:23 +0000 |
| commit | 199dd67c50990a45876b871008cad0dad0f63b88 (patch) | |
| tree | b4fdc0ebd912d6a8f7c1edf18dd2e3e4362b9949 | |
| parent | 5059dda6bd88f60beb925b9c64a458c93af78d0e (diff) | |
add FCPYS and FCPYD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30995 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 5 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 14 |
2 files changed, 16 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 099b499c52..e427050440 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -212,6 +212,11 @@ def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b), "fcmpd $a, $b", [(armcmp DFPRegs:$a, DFPRegs:$b)]>; +// Floating Point Copy +def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>; + +def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>; + // Floating Point Conversion // We use bitconvert for moving the data between the register classes. // The format conversion is done with ARM specific nodes diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index fd04f5aecf..703952367f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -47,9 +47,17 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { - assert (RC == ARM::IntRegsRegisterClass); - BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0) - .addImm(ARMShift::LSL); + assert(RC == ARM::IntRegsRegisterClass || + RC == ARM::FPRegsRegisterClass || + RC == ARM::DFPRegsRegisterClass); + + if (RC == ARM::IntRegsRegisterClass) + BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0) + .addImm(ARMShift::LSL); + else if (RC == ARM::FPRegsRegisterClass) + BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg); + else + BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg); } MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI, |