diff options
| author | Bill Wendling <isanbard@gmail.com> | 2008-10-19 20:34:04 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2008-10-19 20:34:04 +0000 |
| commit | 181b627f62613190322b69b9e73c20a4ec322dba (patch) | |
| tree | 0790f13a2e615640d4e65f0b2848247bcf04215b | |
| parent | 0e3da1def46ae4925d811406f9e67f0c45d5b597 (diff) | |
Fix comment. Other formatting changes. No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57785 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 32540d2a3b..0fba3a403b 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -2207,7 +2207,7 @@ void SelectionDAGLowering::visitUIToFP(User &I) { } void SelectionDAGLowering::visitSIToFP(User &I){ - // UIToFP is never a no-op cast, no need to check + // SIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N)); @@ -3079,6 +3079,7 @@ SelectionDAGLowering::visitLog2(CallInst &I) { void SelectionDAGLowering::visitLog10(CallInst &I) { SDValue result; + if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); @@ -4221,13 +4222,13 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, else if (NumZeroBits >= RegSize-9) isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 else if (NumSignBits > RegSize-16) - isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 + isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 else if (NumZeroBits >= RegSize-17) - isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 + isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 else if (NumSignBits > RegSize-32) - isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 + isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 else if (NumZeroBits >= RegSize-33) - isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 + isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 if (FromVT != MVT::Other) { P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, |