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| author | Evan Cheng <evan.cheng@apple.com> | 2007-07-05 07:17:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-05 07:17:13 +0000 |
| commit | 16b6598325aced8a05ae8c87685d160fe3ad6e66 (patch) | |
| tree | f1d12e7bd20a3b2bb8e17654e186e121990fd166 | |
| parent | ee568cf7948230b78303b86c92722c177d3a5673 (diff) | |
Added ARM::CPSR to represent ARM CPSR status register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37897 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 691514cd8e..3d2646e998 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -78,6 +78,9 @@ def D13 : ARMReg<13, "d13", [S26, S27]>; def D14 : ARMReg<14, "d14", [S28, S29]>; def D15 : ARMReg<15, "d15", [S30, S31]>; +// Current Program Status Register. +def CPSR : ARMReg<0, "cpsr">; + // Register classes. // // pc == Program Counter @@ -188,3 +191,6 @@ def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, // is double-word alignment though. def DPR : RegisterClass<"ARM", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15]>; + +// Condition code registers. +def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; |