diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-08-05 19:40:16 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-08-05 19:40:16 +0000 |
| commit | 14d9495403e4c0129119a79322ee4e744b2eced8 (patch) | |
| tree | dbd7e13b8a2ba785906b977941a2fd0581084cde | |
| parent | f49a23d7a700bc6d0fab434b9df49bc1c2d78da9 (diff) | |
Unbreak the stuff, this is ugly, but we cannot do better for now with 'plain' C calling conv.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78232 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 61a08db29f..252d920e6c 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1460,13 +1460,12 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, } else { TargetRegisterClass *RC; - bool IsHardFloatCC = (CallConv == CallingConv::ARM_AAPCS_VFP); - if (IsHardFloatCC && RegVT == MVT::f32) + if (FloatABIType == FloatABI::Hard && RegVT == MVT::f32) RC = ARM::SPRRegisterClass; - else if (IsHardFloatCC && RegVT == MVT::f64) + else if (FloatABIType == FloatABI::Hard && RegVT == MVT::f64) RC = ARM::DPRRegisterClass; - else if (IsHardFloatCC && RegVT == MVT::v2f64) + else if (FloatABIType == FloatABI::Hard && RegVT == MVT::v2f64) RC = ARM::QPRRegisterClass; else if (AFI->isThumb1OnlyFunction()) RC = ARM::tGPRRegisterClass; @@ -1474,7 +1473,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, RC = ARM::GPRRegisterClass; assert((RegVT == MVT::i32 || RegVT == MVT::f32 || - (IsHardFloatCC && + (FloatABIType == FloatABI::Hard && ((RegVT == MVT::f64) || (RegVT == MVT::v2f64)))) && "RegVT not supported by FORMAL_ARGUMENTS Lowering"); |