diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-14 04:55:10 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-14 04:55:10 +0000 |
| commit | 13664a6194beb70d3efbf318adae5ebe51ddaef8 (patch) | |
| tree | 6a4dd159234d25c27f48b7700aa508ab2e92438e | |
| parent | 03ebd802c7916e126c718ff49b4ebbe449a28c0a (diff) | |
add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/TargetSelectionDAG.td | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index ed63fcbd50..702659a452 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -45,6 +45,10 @@ class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { int OtherOperandNum = OtherOp; } +class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ + int BigOperandNum = BigOp; +} + //===----------------------------------------------------------------------===// // Selection DAG Type Profile definitions. // @@ -77,6 +81,12 @@ def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc SDTCisSameAs<0, 1>, SDTCisFP<0> ]>; +def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround + SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> +]>; +def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend + SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> +]>; def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, SDTCisVTSmallerThanOp<2, 1> @@ -136,6 +146,9 @@ def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; +def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; +def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; + def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; |