remove dead code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24965 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 0 insertions, 37 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index be6b04dfe8..58d547e55d 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -589,12 +589,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
     AddLegalizedOperand(Op.getValue(0), Result);
     AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
     return Result.getValue(Op.ResNo);
-  case ISD::ImplicitDef:
-    Tmp1 = LegalizeOp(Node->getOperand(0));
-    if (Tmp1 != Node->getOperand(0))
-      Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
-                           Tmp1, Node->getOperand(1));
-    break;
   case ISD::UNDEF: {
     MVT::ValueType VT = Op.getValueType();
     switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3438863c90..c17937d05e 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1874,7 +1874,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::TargetConstantPool:  return "TargetConstantPool";
   case ISD::CopyToReg:     return "CopyToReg";
   case ISD::CopyFromReg:   return "CopyFromReg";
-  case ISD::ImplicitDef:   return "ImplicitDef";
   case ISD::UNDEF:         return "undef";
 
   // Unary operators
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 44b38282f0..2ce18e1ae3 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1600,19 +1600,6 @@ void AlphaISel::Select(SDOperand N) {
     return;
   }
 
-  case ISD::ImplicitDef:
-    ++count_ins;
-    Select(N.getOperand(0));
-    switch(N.getValueType()) {
-    case MVT::f32: Opc = Alpha::IDEF_F32; break;
-    case MVT::f64: Opc = Alpha::IDEF_F64; break;
-    case MVT::i64: Opc = Alpha::IDEF_I; break;
-    default: assert(0 && "should have been legalized");
-    };
-    BuildMI(BB, Opc, 0,
-            cast<RegisterSDNode>(N.getOperand(1))->getReg());
-    return;
-
   case ISD::EntryToken: return;  // Noop
 
   case ISD::TokenFactor:
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 7c2b38c51b..a98c275a92 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -2281,13 +2281,6 @@ void ISel::Select(SDOperand N) {
     return;
   }
 
-  case ISD::ImplicitDef: {
-    Select(N.getOperand(0));
-    BuildMI(BB, IA64::IDEF, 0, 
-            cast<RegisterSDNode>(N.getOperand(1))->getReg());
-    return;
-  }
-
   case ISD::BRCOND: {
     MachineBasicBlock *Dest =
       cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 42495bcb56..bae19f8fb7 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1601,16 +1601,6 @@ void ISel::Select(SDOperand N) {
         BuildMI(BB, PPC::OR4, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
     }
     return;
-  case ISD::ImplicitDef:
-    Select(N.getOperand(0));
-    Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
-    if (N.getOperand(1).getValueType() == MVT::i32)
-      BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
-    else if (N.getOperand(1).getValueType() == MVT::f32)
-      BuildMI(BB, PPC::IMPLICIT_DEF_F4, 0, Tmp1);
-    else
-      BuildMI(BB, PPC::IMPLICIT_DEF_F8, 0, Tmp1);
-    return;
   case ISD::RET:
     switch (N.getNumOperands()) {
     default: