diff options
| author | Chris Lattner <sabre@nondot.org> | 2010-03-18 18:10:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-03-18 18:10:56 +0000 |
| commit | 0f53cf22361d89690dcf58409decb43d2a3ad60f (patch) | |
| tree | 13e1cb8f9e4c43935cf7072de0d8c5baa3845569 | |
| parent | 1584390e550b1430fccfd100846844f9fdf6c15b (diff) | |
add a special relocation type for movq loads for object
files that produce special relocation types where the
linker changes movq's into lea's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98839 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86FixupKinds.h | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86MCCodeEmitter.cpp | 15 | ||||
| -rw-r--r-- | test/MC/AsmParser/X86/x86_64-new-encoder.s | 10 |
3 files changed, 23 insertions, 5 deletions
diff --git a/lib/Target/X86/X86FixupKinds.h b/lib/Target/X86/X86FixupKinds.h index c8dac3ce45..a8117d47bf 100644 --- a/lib/Target/X86/X86FixupKinds.h +++ b/lib/Target/X86/X86FixupKinds.h @@ -17,7 +17,8 @@ namespace X86 { enum Fixups { reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch. reloc_pcrel_1byte, // 8-bit pcrel, e.g. branch_1 - reloc_riprel_4byte // 32-bit rip-relative + reloc_riprel_4byte, // 32-bit rip-relative + reloc_riprel_4byte_movq_load // 32-bit rip-relative in movq }; } } diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index 3f18696d85..4547a3a331 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -38,14 +38,15 @@ public: ~X86MCCodeEmitter() {} unsigned getNumFixupKinds() const { - return 3; + return 4; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { const static MCFixupKindInfo Infos[] = { { "reloc_pcrel_4byte", 0, 4 * 8 }, { "reloc_pcrel_1byte", 0, 1 * 8 }, - { "reloc_riprel_4byte", 0, 4 * 8 } + { "reloc_riprel_4byte", 0, 4 * 8 }, + { "reloc_riprel_4byte_movq_load", 0, 4 * 8 } }; if (Kind < FirstTargetFixupKind) @@ -197,6 +198,14 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, "Invalid rip-relative address"); EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS); + unsigned FixupKind = X86::reloc_riprel_4byte; + + // movq loads are handled with a special relocation form which allows the + // linker to eliminate some loads for GOT references which end up in the + // same linkage unit. + if (MI.getOpcode() == X86::MOV64rm_TC) + FixupKind = X86::reloc_riprel_4byte_movq_load; + // rip-relative addressing is actually relative to the *next* instruction. // Since an immediate can follow the mod/rm byte for an instruction, this // means that we need to bias the immediate field of the instruction with @@ -204,7 +213,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, // expression to emit. int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0; - EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_riprel_4byte), + EmitImmediate(Disp, 4, MCFixupKind(FixupKind), CurByte, OS, Fixups, -ImmSize); return; } diff --git a/test/MC/AsmParser/X86/x86_64-new-encoder.s b/test/MC/AsmParser/X86/x86_64-new-encoder.s index 797558a81e..712803e41f 100644 --- a/test/MC/AsmParser/X86/x86_64-new-encoder.s +++ b/test/MC/AsmParser/X86/x86_64-new-encoder.s @@ -25,5 +25,13 @@ movq $12, foo(%rip) // CHECK: encoding: [0x48,0xc7,0x05,A,A,A,A,0x0c,0x00,0x00,0x00] // CHECK: fixup A - offset: 3, value: foo-8, kind: reloc_riprel_4byte -// CHECK: addq $-424, %rax # encoding: [0x48,0x05,0x58,0xfe,0xff,0xff] +// CHECK: addq $-424, %rax +// CHECK: encoding: [0x48,0x05,0x58,0xfe,0xff,0xff] addq $-424, %rax + + +// CHECK: movq _foo@GOTPCREL(%rip), %rax +// CHECK: encoding: [0x48,0x8b,0x05,A,A,A,A] +// CHECK: fixup A - offset: 3, value: _foo@GOTPCREL, kind: reloc_riprel_4byte_movq_load +movq _foo@GOTPCREL(%rip), %rax + |