diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2010-02-16 22:01:59 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-02-16 22:01:59 +0000 |
| commit | 0eb0c7401c34c0b4604f732ce54db995eead14e6 (patch) | |
| tree | cae63729baa812954a82059fbfd1276506bed956 | |
| parent | 0296f3e50446094f5c484e155e8c1838eb9f5a0c (diff) | |
Handle tGPR register class in a few more places. This fixes some llvm-gcc
build failures due to my fix for pr6111.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96402 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 7b35a06b94..ae84da8af2 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -704,6 +704,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MFI.getObjectSize(FI), Align); + // tGPR is used sometimes in ARM instructions that need to avoid using + // certain registers. Just treat it as GPR here. + if (RC == ARM::tGPRRegisterClass) + RC = ARM::GPRRegisterClass; + if (RC == ARM::GPRRegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) .addReg(SrcReg, getKillRegState(isKill)) @@ -752,6 +757,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MFI.getObjectSize(FI), Align); + // tGPR is used sometimes in ARM instructions that need to avoid using + // certain registers. Just treat it as GPR here. + if (RC == ARM::tGPRRegisterClass) + RC = ARM::GPRRegisterClass; + if (RC == ARM::GPRRegisterClass) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)); |