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authorJim Grosbach <grosbach@apple.com>2010-09-08 00:26:59 +0000
committerJim Grosbach <grosbach@apple.com>2010-09-08 00:26:59 +0000
commit0cfcf93c95af91e809ef740eb0ab368477226b40 (patch)
treea8bca8406e7f2727279581d0b0470e9435116399
parent72db18243839860019ab93e7c30e86228f017ea7 (diff)
correct spill code to properly determine if dynamic stack realignment is
present in the function and thus whether aligned load/store instructions can be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113323 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 79e9a58892..a7edea5dbf 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -748,7 +748,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
case ARM::QPR_VFP2RegClassID:
case ARM::QPR_8RegClassID:
// FIXME: Neon instructions should support predicates
- if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q))
.addFrameIndex(FI).addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
@@ -846,7 +846,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
case ARM::QPRRegClassID:
case ARM::QPR_VFP2RegClassID:
case ARM::QPR_8RegClassID:
- if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
+ if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg)
.addFrameIndex(FI).addImm(16)
.addMemOperand(MMO));