diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-12-12 21:21:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-12-12 21:21:32 +0000 |
| commit | 0ca67332fa4eaed35e8e85b2c935500798ea6c2a (patch) | |
| tree | 9134773831227ee32eb674b908976e27a6c272e9 | |
| parent | c35010d3a44397dd04ed3bff5287f9c718dacd4a (diff) | |
Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32493 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index c6ca13e2a3..c112b873b7 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3942,6 +3942,9 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V, else Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op); return DAG.getCopyToReg(getRoot(), Reg, Op); + } else if (SrcVT == MVT::f32 || SrcVT == MVT::f64) { + return DAG.getCopyToReg(getRoot(), Reg, + DAG.getNode(ISD::BIT_CONVERT, DestVT, Op)); } else { // The src value is expanded into multiple registers. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, |