diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2010-05-07 01:54:08 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-07 01:54:08 +0000 |
| commit | 07a6d9391c74117ae79f832fd840deacab737b40 (patch) | |
| tree | 268cc1a88699d4777f8ef6f45ae76088291c892d | |
| parent | 403d312c0ffefdd0f54eed5e5ddcf163533f9103 (diff) | |
Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103234 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 427123b876..eff2008e61 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -782,11 +782,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI); AddDefaultPred(MIB.addMemOperand(MMO)); } else { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) - .addReg(SrcReg, getKillRegState(isKill)) - .addFrameIndex(FI) - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) - .addMemOperand(MMO)); + MachineInstrBuilder MIB = + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) + .addFrameIndex(FI) + .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) + .addMemOperand(MMO); + MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI); + AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI); + } } else { assert((RC == ARM::QQPRRegisterClass || @@ -838,10 +841,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI); AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO)); } else { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) - .addFrameIndex(FI) - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) - .addMemOperand(MMO)); + MachineInstrBuilder MIB = + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) + .addFrameIndex(FI) + .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) + .addMemOperand(MMO); + MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI); + AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI); } } else { assert((RC == ARM::QQPRRegisterClass || |