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authorJim Grosbach <grosbach@apple.com>2010-11-19 23:14:43 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-19 23:14:43 +0000
commit078e239f6948d4a942e16db3868908e503a51efb (patch)
tree179b0e7ac752d4d4452d13d0dc85bc436234ff43
parent1228038ed93504b0a34878dc659cca98092a1f2d (diff)
Fix ARM LDR* post-indexed operand encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119869 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 636801b09a..c1ac9c56c3 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1637,13 +1637,13 @@ multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
(ins GPR:$Rn, am3offset:$offset), IndexModePost,
LdMiscFrm, itin,
opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
- bits<10> addr;
+ bits<10> offset;
bits<4> Rn;
- let Inst{23} = addr{8}; // U bit
- let Inst{22} = addr{9}; // 1 == imm8, 0 == Rm
+ let Inst{23} = offset{8}; // U bit
+ let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
let Inst{19-16} = Rn;
- let Inst{11-8} = addr{7-4}; // imm7_4/zero
- let Inst{3-0} = addr{3-0}; // imm3_0/Rm
+ let Inst{11-8} = offset{7-4}; // imm7_4/zero
+ let Inst{3-0} = offset{3-0}; // imm3_0/Rm
}
}