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authorEric Christopher <echristo@gmail.com>2012-11-14 22:09:20 +0000
committerEric Christopher <echristo@gmail.com>2012-11-14 22:09:20 +0000
commit06b423452c85f5a78a1b0555b767cf27b36c0752 (patch)
treeb13a40fe82d2f68d333a99fe3ce43d970217caf6
parentac99eed043e84905bc2fb299ccaf5809e9c0e90f (diff)
Remove the CellSPU port.
Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--autoconf/configure.ac6
-rwxr-xr-xconfigure10
-rw-r--r--docs/CodeGenerator.rst9
-rw-r--r--include/llvm/ADT/Triple.h1
-rw-r--r--include/llvm/Intrinsics.td1
-rw-r--r--include/llvm/IntrinsicsCellSPU.td242
-rw-r--r--lib/Support/Triple.cpp8
-rw-r--r--lib/Target/CellSPU/CMakeLists.txt30
-rw-r--r--lib/Target/CellSPU/CellSDKIntrinsics.td449
-rw-r--r--lib/Target/CellSPU/LLVMBuild.txt32
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt6
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/LLVMBuild.txt23
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/Makefile16
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp43
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h30
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp94
-rw-r--r--lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h38
-rw-r--r--lib/Target/CellSPU/Makefile20
-rw-r--r--lib/Target/CellSPU/README.txt106
-rw-r--r--lib/Target/CellSPU/SPU.h31
-rw-r--r--lib/Target/CellSPU/SPU.td66
-rw-r--r--lib/Target/CellSPU/SPU128InstrInfo.td41
-rw-r--r--lib/Target/CellSPU/SPU64InstrInfo.td408
-rw-r--r--lib/Target/CellSPU/SPUAsmPrinter.cpp333
-rw-r--r--lib/Target/CellSPU/SPUCallingConv.td53
-rw-r--r--lib/Target/CellSPU/SPUFrameLowering.cpp256
-rw-r--r--lib/Target/CellSPU/SPUFrameLowering.h80
-rw-r--r--lib/Target/CellSPU/SPUHazardRecognizers.cpp135
-rw-r--r--lib/Target/CellSPU/SPUHazardRecognizers.h37
-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp1192
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp3267
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.h178
-rw-r--r--lib/Target/CellSPU/SPUInstrBuilder.h43
-rw-r--r--lib/Target/CellSPU/SPUInstrFormats.td320
-rw-r--r--lib/Target/CellSPU/SPUInstrInfo.cpp449
-rw-r--r--lib/Target/CellSPU/SPUInstrInfo.h84
-rw-r--r--lib/Target/CellSPU/SPUInstrInfo.td4484
-rw-r--r--lib/Target/CellSPU/SPUMachineFunction.cpp14
-rw-r--r--lib/Target/CellSPU/SPUMachineFunction.h50
-rw-r--r--lib/Target/CellSPU/SPUMathInstr.td97
-rw-r--r--lib/Target/CellSPU/SPUNodes.td159
-rw-r--r--lib/Target/CellSPU/SPUNopFiller.cpp153
-rw-r--r--lib/Target/CellSPU/SPUOperands.td664
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.cpp357
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.h106
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.td183
-rw-r--r--lib/Target/CellSPU/SPURegisterNames.h19
-rw-r--r--lib/Target/CellSPU/SPUSchedule.td59
-rw-r--r--lib/Target/CellSPU/SPUSelectionDAGInfo.cpp23
-rw-r--r--lib/Target/CellSPU/SPUSelectionDAGInfo.h31
-rw-r--r--lib/Target/CellSPU/SPUSubtarget.cpp65
-rw-r--r--lib/Target/CellSPU/SPUSubtarget.h97
-rw-r--r--lib/Target/CellSPU/SPUTargetMachine.cpp94
-rw-r--r--lib/Target/CellSPU/SPUTargetMachine.h96
-rw-r--r--lib/Target/CellSPU/TargetInfo/CMakeLists.txt7
-rw-r--r--lib/Target/CellSPU/TargetInfo/CellSPUTargetInfo.cpp20
-rw-r--r--lib/Target/CellSPU/TargetInfo/LLVMBuild.txt23
-rw-r--r--lib/Target/CellSPU/TargetInfo/Makefile15
-rw-r--r--lib/Target/LLVMBuild.txt2
-rw-r--r--test/CodeGen/CellSPU/2009-01-01-BrCond.ll31
-rw-r--r--test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll28
-rw-r--r--test/CodeGen/CellSPU/and_ops.ll282
-rw-r--r--test/CodeGen/CellSPU/arg_ret.ll34
-rw-r--r--test/CodeGen/CellSPU/bigstack.ll17
-rw-r--r--test/CodeGen/CellSPU/bss.ll11
-rw-r--r--test/CodeGen/CellSPU/call.ll49
-rw-r--r--test/CodeGen/CellSPU/crash.ll8
-rw-r--r--test/CodeGen/CellSPU/ctpop.ll30
-rw-r--r--test/CodeGen/CellSPU/div_ops.ll22
-rw-r--r--test/CodeGen/CellSPU/dp_farith.ll102
-rw-r--r--test/CodeGen/CellSPU/eqv.ll152
-rw-r--r--test/CodeGen/CellSPU/extract_elt.ll277
-rw-r--r--test/CodeGen/CellSPU/fcmp32.ll36
-rw-r--r--test/CodeGen/CellSPU/fcmp64.ll7
-rw-r--r--test/CodeGen/CellSPU/fdiv.ll22
-rw-r--r--test/CodeGen/CellSPU/fneg-fabs.ll42
-rw-r--r--test/CodeGen/CellSPU/i64ops.ll57
-rw-r--r--test/CodeGen/CellSPU/i8ops.ll25
-rw-r--r--test/CodeGen/CellSPU/icmp16.ll574
-rw-r--r--test/CodeGen/CellSPU/icmp32.ll575
-rw-r--r--test/CodeGen/CellSPU/icmp64.ll146
-rw-r--r--test/CodeGen/CellSPU/icmp8.ll446
-rw-r--r--test/CodeGen/CellSPU/immed16.ll40
-rw-r--r--test/CodeGen/CellSPU/immed32.ll83
-rw-r--r--test/CodeGen/CellSPU/immed64.ll95
-rw-r--r--test/CodeGen/CellSPU/int2fp.ll41
-rw-r--r--test/CodeGen/CellSPU/intrinsics_branch.ll150
-rw-r--r--test/CodeGen/CellSPU/intrinsics_float.ll94
-rw-r--r--test/CodeGen/CellSPU/intrinsics_logical.ll49
-rw-r--r--test/CodeGen/CellSPU/jumptable.ll21
-rw-r--r--test/CodeGen/CellSPU/lit.local.cfg6
-rw-r--r--test/CodeGen/CellSPU/loads.ll59
-rw-r--r--test/CodeGen/CellSPU/mul-with-overflow.ll15
-rw-r--r--test/CodeGen/CellSPU/mul_ops.ll88
-rw-r--r--test/CodeGen/CellSPU/nand.ll125
-rw-r--r--test/CodeGen/CellSPU/or_ops.ll278
-rw-r--r--test/CodeGen/CellSPU/private.ll19
-rw-r--r--test/CodeGen/CellSPU/rotate_ops.ll172
-rw-r--r--test/CodeGen/CellSPU/select_bits.ll572
-rw-r--r--test/CodeGen/CellSPU/sext128.ll71
-rw-r--r--test/CodeGen/CellSPU/shift_ops.ll348
-rw-r--r--test/CodeGen/CellSPU/shuffles.ll69
-rw-r--r--test/CodeGen/CellSPU/sp_farith.ll90
-rw-r--r--test/CodeGen/CellSPU/stores.ll181
-rw-r--r--test/CodeGen/CellSPU/storestruct.ll13
-rw-r--r--test/CodeGen/CellSPU/struct_1.ll147
-rw-r--r--test/CodeGen/CellSPU/sub_ops.ll26
-rw-r--r--test/CodeGen/CellSPU/trunc.ll94
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/README.txt5
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/i32operations.c69
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/i64operations.c673
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/i64operations.h43
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg1
-rw-r--r--test/CodeGen/CellSPU/useful-harnesses/vecoperations.c179
-rw-r--r--test/CodeGen/CellSPU/v2f32.ll78
-rw-r--r--test/CodeGen/CellSPU/v2i32.ll61
-rw-r--r--test/CodeGen/CellSPU/vec_const.ll154
-rw-r--r--test/CodeGen/CellSPU/vecinsert.ll131
-rw-r--r--utils/lit/lit/ExampleTests/LLVM.InTree/test/site.exp2
-rw-r--r--utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/site.exp2
120 files changed, 9 insertions, 22263 deletions
diff --git a/autoconf/configure.ac b/autoconf/configure.ac
index f1842a6d8a..0a7c6e2912 100644
--- a/autoconf/configure.ac
+++ b/autoconf/configure.ac
@@ -697,14 +697,14 @@ dnl Allow specific targets to be specified for building (or not)
TARGETS_TO_BUILD=""
AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets],
[Build specific host targets: all or target1,target2,... Valid targets are:
- host, x86, x86_64, sparc, powerpc, arm, mips, spu, hexagon,
+ host, x86, x86_64, sparc, powerpc, arm, mips, hexagon,
xcore, msp430, nvptx, and cpp (default=all)]),,
enableval=all)
if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -716,7 +716,6 @@ case "$enableval" in
mipsel) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64el) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
- spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -731,7 +730,6 @@ case "$enableval" in
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
diff --git a/configure b/configure
index d4a42f70ff..de0dd4821c 100755
--- a/configure
+++ b/configure
@@ -1426,8 +1426,8 @@ Optional Features:
YES)
--enable-targets Build specific host targets: all or
target1,target2,... Valid targets are: host, x86,
- x86_64, sparc, powerpc, arm, mips, spu, hexagon,
- xcore, msp430, nvptx, and cpp (default=all)
+ x86_64, sparc, powerpc, arm, mips, hexagon, xcore,
+ msp430, nvptx, and cpp (default=all)
--enable-experimental-targets
Build experimental host targets: disable or
target1,target2,... (default=disable)
@@ -5418,7 +5418,7 @@ if test "$enableval" = host-only ; then
enableval=host
fi
case "$enableval" in
- all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
+ all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;;
*)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do
case "$a_target" in
x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;;
@@ -5430,7 +5430,6 @@ case "$enableval" in
mipsel) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
mips64el) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
- spu) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
xcore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
msp430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;;
@@ -5445,7 +5444,6 @@ case "$enableval" in
ARM) TARGETS_TO_BUILD="ARM $TARGETS_TO_BUILD" ;;
Mips) TARGETS_TO_BUILD="Mips $TARGETS_TO_BUILD" ;;
MBlaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;;
- CellSPU|SPU) TARGETS_TO_BUILD="CellSPU $TARGETS_TO_BUILD" ;;
XCore) TARGETS_TO_BUILD="XCore $TARGETS_TO_BUILD" ;;
MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;;
Hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;;
@@ -10315,7 +10313,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<EOF
-#line 10318 "configure"
+#line 10316 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst
index 5fab76ec1a..21af969d42 100644
--- a/docs/CodeGenerator.rst
+++ b/docs/CodeGenerator.rst
@@ -1762,7 +1762,6 @@ Here is the table:
:raw-html:`<tr>`
:raw-html:`<th>Feature&