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authorEvan Cheng <evan.cheng@apple.com>2006-01-25 18:52:42 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-01-25 18:52:42 +0000
commit0577a22c678bd5e31047e6b8038c6917202271ee (patch)
tree4004b940607d924b7a0f13339e6e3997014ae415
parentacc398c195a697795bff3245943d104eb19192b9 (diff)
Set SchedulingForLatency to be the default scheduling preference for all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25607 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp1
-rw-r--r--lib/Target/IA64/IA64ISelLowering.cpp1
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp1
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp1
-rw-r--r--lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp1
5 files changed, 1 insertions, 4 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index cffdc0e5c1..1128f74fa6 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -32,6 +32,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
UseUnderscoreSetJmpLongJmp = false;
IntDivIsCheap = false;
Pow2DivIsCheap = false;
+ SchedPreferenceInfo = SchedulingForLatency;
}
TargetLowering::~TargetLowering() {}
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index c963bfc5a6..b6cd9b08f7 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -100,7 +100,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
- setSchedulingPreference(SchedulingForLatency);
setStackPointerRegisterToSaveRestore(IA64::r12);
computeRegisterProperties();
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index df69a84acb..b9949590a2 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -150,7 +150,6 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
}
setSetCCResultContents(ZeroOrOneSetCCResult);
- setSchedulingPreference(SchedulingForLatency);
setStackPointerRegisterToSaveRestore(PPC::R1);
computeRegisterProperties();
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index c5b282db6c..d8e6fb469e 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -167,7 +167,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
- setSchedulingPreference(SchedulingForLatency);
setStackPointerRegisterToSaveRestore(V8::O6);
computeRegisterProperties();
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index c5b282db6c..d8e6fb469e 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -167,7 +167,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
- setSchedulingPreference(SchedulingForLatency);
setStackPointerRegisterToSaveRestore(V8::O6);
computeRegisterProperties();