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authorJim Grosbach <grosbach@apple.com>2010-11-18 18:01:40 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-18 18:01:40 +0000
commit056ab107ff8e818258c39b1f1e318b2aa1a417fc (patch)
tree34c06e3d5a408c0c8d998df00b83dab3858e5363
parent4229c62dcfb6a02d5d93ca9f022910dced77dcb0 (diff)
ARMPseudoInst instructions should default to being considered a single 4-byte
instruction. Any that may be expanded otherwise by MC lowering should override this value. rdar://8683274 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119713 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrFormats.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index e84b98d100..3533ce6859 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -249,6 +249,9 @@ class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
class ARMPseudoInst<dag oops, dag iops, InstrItinClass itin,
list<dag> pattern>
: PseudoInst<oops, iops, itin, pattern> {
+ // Default these to 4byte size, as they're almost always expanded to a
+ // single instruction. Any exceptions can override the SZ field value.
+ let SZ = Size4Bytes;
list<Predicate> Predicates = [IsARM];
}