diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-01-05 16:09:16 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-01-05 16:09:16 +0000 |
| commit | 0539313fe5b9d9050cc23b245cfe213b927a296b (patch) | |
| tree | 7ede32d564fdb9d2e6421a996f1ee623c525a977 | |
| parent | 2dcb9688bb089841ccbfc08a8c7cee39047f4a84 (diff) | |
Minor optimization to allocate R8 registers in a better order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19289 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 1d86c0e643..f0ab68d4c9 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -61,7 +61,13 @@ let Namespace = "X86" in { // top-level register classes. The order specified in the register list is // implicitly defined to be the register allocation order. // -def R8 : RegisterClass<i8, 8, [AL, AH, CL, CH, DL, DH, BL, BH]>; + +// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false +// dependences between upper and lower parts of the register. BL and BH are +// last because they are call clobbered. Both Athlon and P4 chips suffer this +// issue. +def R8 : RegisterClass<i8, 8, [AL, CL, DL, AH, CH, DH, BL, BH]>; + def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { |